High-Speed Data Conversion for Digital Ultra-Wideband Radio Receivers

Ultra wideband radio (UWB) is a new high-speed wireless technology that uses subnanosecond pulses to transmit information. Implementing an all-digital UWB receiver has numerous benefits ranging from low cost and ease of design to flexibility. Digitizing an RF signal near the antenna, however, introduces its own set of challenges and has traditionally been considered infeasible. A high-speed, high-resolution analog-digital converter (ADC) is difficult to design, and is extremely power-hungry. However, due to the unique spectral characteristics of UWB signals and their noise enviroment, it can be shown that reliable detection of a UWB signal is achievable with very few bits of resolution in the ADC. In this thesis, the role of quantization noise in UWB systems is analyzed and the sufficiency of 4 bits of precision is demonstrated. Data conversion at several gigasamples/sec (GSPS) is nevertheless challenging, even at low resolutions. The feasibility of this problem has been investigated through the design and implementation of a 4-bit, 4 GSPS ADC for a prototype UWB system, using a 0.18 μm CMOS process. A time-interleaved architecture was chosen, with 4 FLASH channels each running at 1 GHz using offset clocks. The desired resolution was achieved through careful device sizing in the preamplifier and comparators rather than relying on complex calibration schemes. Simulation results and chip measurements are presented. The design meets the desired 4 GSPS sampling rate and 4-bit precision in simulation. The fabricated chip achieves 2.9 effective bits of resolution at 1.5 GSPS and appears to have reasonable dynamic performance. Its total power consumption at this rate is 217mW. Testing at the full designed speed was not possible due to problems with the on-chip test interface but these have been identified. This work demonstrates that the problem of high-speed data conversion for digital UWB receivers is tractable in CMOS within a reasonable power budget. Thesis Supervisor: Anantha P. Chandrakasan Title: Professor of Electrical Engineering and Computer Science